Main Program
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Monday, 24th, June, 2013
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PM
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7:00-9:00
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Reception at David Intercontinental
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Tuesday, 25th June, 2013
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AM
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9:00-9:15
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Welcome Remarks
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9:15-10:15
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Keynote: Dr. Dileep Bhandarkar, VP Technology, Qualcomm Technologies Inc — “My 40 year Journey from Mainframes to Smart Phones” (pdf)
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10:15-10:45
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Coffee break
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10:45-12:35
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Session 1A: Accelerators and Emerging Architectures
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Session 1B: DRAM and Memory Controller Issues
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PM
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12:35-2:00
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Lunch
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2:00-3:15
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Section 2A: Virtualization
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Session 2B: Heterogeneous and Fine-Grained Architectures
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3:15-3:45
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Coffee break
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3:45-5:00
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Session 3A: Emerging Technologies
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Session 3B: Memory Consistency and Transactions
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5:30-6:30
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Business Meeting
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Wednesday June 26, 2013
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AM
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8:30-10:10
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Session 4A: Big Data
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Session 4B: Power and Energy
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10:10-10:40
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Coffee break
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10:40-12:30
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Session 5A: GPUs
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Session 5B Memory
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PM
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12:30-2:30
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Awards Lunch
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2:30-onwards
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Excursion Banquet
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Thursday, June 27, 2013
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AM
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9:00-10:00
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Keynote: Prof. Uri Weiser – Technion Israel, “The next frontier in Computer Architecture – Heterogeneous and Memory Intensive Architecture”
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10:00-10:30
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Coffee break
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10:30-12:10
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Session 6A: Non-Volatile Storage
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Session 6B: Simulation and Analysis Techniques
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PM
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12:10-1:30
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Lunch
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1:30-2:45
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Session 7A: Cache Coherence
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Session 7B: Security
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2:45-3:15
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Coffee break
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3:15-4:30
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Session 8A: Data Centers
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Session 8B: Reliability and Debugging
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4:30-4:45
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Closing Remarks
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Full Program
Monday, June 24, 2013
7-9PM: Registration and Welcome cocktail at David Intercontinental
Tuesday June 25, 2013
9-9:15am: Welcome Remarks
9:15-10:10am: Keynote 1 – Dr. Dileep Bhandarkar, Qualcomm — “My 40 year Journey from Mainframes to Smart Phones”
10:45am-12:35pm
Session 1A: Accelerators and Emerging Architectures
Chair: Simha Sethumadhavan, Columbia University
Continuous Real-World Inputs Can Open Up Alternative Accelerator Designs
Bilel Belhadj, CEA
Antoine Joubert, CEA
Zheng Li, INRIA
Rodolphe Heliot, CEA
Olivier Temam, INRIA
Flicker: A Dynamically Adaptive Architecture for Power Limited Multicore Systems
Paula Petrica, Intel Corporation
Adam M. Izraelevitz, Cornell University
David H. Albonesi, Cornell University
Christine A. Shoemaker, Cornell University
Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing
Wajahat Qadeer, Stanford University
Rehan Hameed, Stanford University
Ofer Shacham, Stanford University
Preethi Venkatesan, Stanford University
Christos Kozyrakis, Stanford University
Mark Horowitz, Stanford University
Thin Servers with Smart Pipes: Designing SoC Accelerators for Memcached
Kevin Lim, HP Labs
David Meisner, Facebook
Ali Saidi, ARM
Parthasarathy Ranganathan, HP Labs
Thomas F. Wenisch, University of Michigan
Session 1B: DRAM and Memory Controller Issues
Chair: David Wentzlaff, Princeton University
Understanding and Mitigating Refresh Overheads in High-Density DDR-4 DRAM Systems
Janani Mukundan, Cornell University
Hillery Hunter, IBM Research
Kyu-Hyoun Kim, IBM Research
Jeffrey Stuecheli, IBM Server & Technology Group
José F. Martínez, Cornell University
An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms
Jamie Liu, Carnegie Mellon University
Ben Jaiyen, Carnegie Mellon University
Yoongu Kim, Carnegie Mellon University
Chris Wilkerson, Intel Corporation
Onur Mutlu, Carnegie Mellon University
ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error-Rates
Prashant Nair, Georgia Tech
Daehyun Kim, Georgia Tech
Moinuddin Qureshi, Georgia Tech
Improving Memory Scheduling via Processor-Side Load Criticality Information
Saugata Ghose, Cornell University
Hyodong Lee, Cornell University
José F. Martínez, Cornell University
Tuesday 2pm-3:15pm
Section 2A: Virtualization
Chair: Natalie Enright Jerger, University of Toronto
Agile, Efficient Virtualization Power Management with Low-latency Server Power States
Canturk Isci, IBM
Suzanne McIntosh, IBM
Jeffrey O. Kephart, IBM
Rajarshi Das, IBM
James Hanson, IBM
Scott Piper, IBM
Robert Wolford, IBM
Tom Brey, IBM
Robert Kanter, IBM
Allen Ng, IBM
James Norris, IBM
Abdoulaye Traore, IBM
Michael Frissora, IBM
Secure I/O Device Sharing among Virtual Machines on Multiple Hosts
Cheng-Chun Tu, State University of New York at Stony Brook
Chao-tang Lee, Industrial Technology Research Institute, Taiwan
Tzi-cker Chiueh, Industrial Technology Research Institute, Taiwan
Improving Virtualization in the Presence of Software Managed Translation Look-aside Buffers
Xiaotao Chang, IBM Research
Hubertus Franke, IBM Research
Ge Yi, IBM Research
Tao Liu, IBM Research
Kun Wang, IBM Research
Jimi Xenidis, Qualcomm Research
Fei Chen, IBM Research
Yu Zhang, IBM Research
Session 2B: Heterogeneous and Fine-Grained Architectures
Chair: Debbie Marr, Intel
Microarchitectural Mechanisms to Exploit Value Structure in SIMT Architectures
Ji Kim, Cornell University
Christopher Torng, Cornell University
Shreesha Srinath, Cornell University
Derek Lockhart, Cornell University
Christopher Batten, Cornell University
Triggered Instructions: A Control Paradigm for Spatially-Programmed Architectures
Angshuman Parashar, Intel
Michael Pellauer, Intel
Michael Adler, Intel
Bushra Ahsan, Intel
Neal Crago, Intel
Daniel Lustig, Princeton University
Vladimir Pavlov, Intel
Antonia Zhai, Intel, University of Minnesota
Mohit Gambhir, Intel
Aamer Jaleel, Intel
Randy Allmon, Intel
Rachid Rayess, Intel
Stephen Maresh, Intel
Joel Emer, Intel/MIT
Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs
Jose A. Joao, University of Texas at Austin
M. Aater Suleman, Calxeda Inc.
Onur Mutlu, Carnegie Mellon University
Yale N. Patt, University of Texas at Austin
Tuesday 3:45pm-5pm
Session 3A: Emerging Technologies
Chair: Mikko Lipasti, U. Wisconsin
Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers
Daniel Kudrow, UC Santa Barbara
Kenneth Bier, UC Santa Barbara
Zhaoxia Deng, UC Santa Barbara
Diana Franklin, UC Santa Barbara
Yu Tomita, Georgia Institute of Technology
Kenneth Brown, Georgia Institute of Technology
Frederic Chong, UC Santa Barbara
DNA-based Molecular Architecture with Spatially Localized Components
Richard Muscat, University of Washington
Karin Strauss, Microsoft Research and University of Washington
Luis Ceze, University of Washington
Georg Seelig, University of Washington
AC-DIMM: Associative Computing with STT-MRAM
Qing Guo, University of Rochester
Xiaochen Guo, University of Rochester
Ravi Petel, University of Rochester
Engin Ipek, University of Rochester
Eby. G Friedman, University of Rochester
Session 3B: Memory Consistency and Transactions
Chair: Steve Keckler, NVIDIA / University of Texas
Exploring Memory Consistency for Massively-Threaded Throughput-Oriented Processors
Blake A. Hechtman, Duke University, AMD
Daniel J. Sorin, Duke University
WeeFence: Toward Making Fences Free in TSO
Yuelu Duan, University of Illinois
Abdullah Muzahid, University of Texas at San Antonio
Josep Torrellas, University of Illinois
Robust Architectural Support for Transactional Memory in the POWER Architecture
Harold W. Cain, IBM Research
Brad Frey, IBM Systems and Technology Group
Derek Williams, IBM Systems and Technology Group
Maged Michael, IBM Research
Cathy May, IBM Systems and Technology Group
Hung Le, IBM Systems and Technology Group
5:30-6:30pm: Business Meeting
Wednesday June 26, 2013
8:30am-10:10am
Session 4A: Big Data
Chair: Canturk Isci, IBM Research
Efficient Virtual Memory for Big Memory Servers
Arkaprava Basu, University of Wisconsin, Madison
Jayneel Gandhi, University of Wisconsin, Madison
Jichuan Chang, HP Labs
Mark Hill, University of Wisconsin, Madison
Mike Swift, University of Wisconsin, Madison
Navigating Big Data with High-Throughput, Energy-Efficient Data Partitioning
Lisa K. Wu, Columbia University
Raymond J. Barker, Columbia University
Martha A. Kim, Columbia University
Kenneth A. Ross, Columbia University
LINQits: Big Data on Little Clients
Eric Chung, Microsoft Research Silicon Valley
John Davis, Microsoft Research Silicon Valley
Jaewon Lee, POSTECH
STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution
Islam Atta, University of Toronto
Pinar Tözün, Ecole Polytechnique Federale de Lausanne
Xin Tong, University of Toronto
Anastasia Ailamaki, Ecole Polytechnique Federale de Lausanne
Andreas Moshovos, University of Toronto
Session 4B: Power and Energy
Chair: John Kim, KAIST
Cooperative Boosting: Needy Versus Greedy Power Management
Indrani Paul, AMD Research, Georgia Institute of Technology
Srilatha Manne, AMD Research
Manish Arora, AMD Research, University of California San Diego
William L. Bircher, AMD Research
Sudhakar Yalamanchili, Georgia Institute of Technology
Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors
Anys Bacha, The Ohio State University
Radu Teodorescu, The Ohio State University
A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness
Henry Cook, UC Berkeley
Miquel Moreto, ICSI/UC Berkeley/UPC
Sarah Bird, UC Berkeley
Khanh Ngoc Dao, UC Berkeley
David Patterson, UC Berkeley
Krste Asanovic, UC Berkeley
Catnap: Energy Proportional Multiple Network-on-Chip
Reetuparna Das, University of Michigan
Satish Narayanasamy, University of Michigan
Sudhir Satpathy, University of Michigan
Ronald Dreslinski, University of Michigan
Wednesday: 10:40am-12:30pm
Session 5A: GPUs
Chair: Christopher Batten, Cornell University
Orchestrated Scheduling and Prefetching for GPGPUs
Adwait Jog, The Pennsylvania State University
Onur Kayiran, The Pennsylvania State University
Asit K. Mishra, Intel Labs
Mahmut T. Kandemir, The Pennsylvania State University
Onur Mutlu, Carnegie Mellon University
Ravishankar Iyer, Intel Labs
Chita R. Das, The Pennsylvania State University
An Energy Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU
Naifeng Jing, Shanghai Jiao Tong University
Yao Shen, Shanghai Jiao Tong University
Yao Lu, Shanghai Jiao Tong University
Shrikanth Ganapathy, Universitat Politecnica de Catalunya
Zhigang Mao, Shanghai Jiao Tong University
Minyi Guo, Shanghai Jiao Tong University
Ramon Canal, Universitat Politecnica de Catalunya
Xiaoyao Liang, Shanghai Jiao Tong University
Maximizing SIMD Resource Utilization in GPGPUs with SIMD Lane Permutation
Minsoo Rhu, The University of Texas at Austin
Mattan Erez, The University of Texas at Austin
SIMD Divergence Optimization through Intra-Warp Compaction
Aniruddha Vaidya, Intel
Anahita Shayesteh, Intel
Dong Hyuk Woo, Intel
Roy Saharoy, Intel
Mani Azimi, Intel
Session 5B: Memory
Chair: Karin Strauss, Microsoft Research
Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations
Jung Ho Ahn, Seoul National University
Jae W. Lee, Sungkyunkwan University
Seongil O, Seoul National University
Yuhwan Ro, Seoul National University
Young Hoon Son, Seoul National University and Samsung Electronics
CPU Transparent Protection of OS Kernel and Hypervisor Integrity with Programmable DRAM
Ziyi Liu, University of Houston
Jonghyuk Lee, University of Houston
Junyuan Zeng, University of Texas at Dallas
Yuanfeng Wen, University of Houston
Zhiqiang Lin, University of Texas at Dallas
Weidong Shi, University of Houston
Die-Stacked DRAM Caches for Servers: Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache
Djordje Jevdjic, EPFL
Stavros Volos, EPFL
Babak Falsafi, EPFL
Resilient Die-stacked DRAM Caches
Jaewoong Sim, Georgia Institute of Technology
Gabriel H. Loh, AMD
Vilas Sridharan, AMD
Mike O'Connor, AMD
12:30-2:30pm: Awards Lunch
2:30-onwards: Excursion Banquet
Thursday, June 27, 2013
9-10am: Keynote 2: Prof. Uri Weiser – Technion Israel, “The next frontier in Computer Architecture – Heterogeneous and Memory Intensive Architecture”
10:30am-12:10pm
Session 6A: Non-Volatile Storage
Chair: Gabriel Loh, AMD Research
Bit Mapping for Balanced PCM Cell Programming
Yu Du, University of Pittsburgh
Miao Zhou, University of Pittsburgh
Bruce Childers, University of Pittsburgh
Daniel Mosse, University of Pittsburgh
Rami Melhem, University of Pittsburgh
Tri-Level-Cell Phase Change Memory: Toward an Efficient and Reliable Memory System
Nak Hee Seong, Georgia Institute of Technology
Sungkap Yeo, Georgia Institute of Technology
Hsien-Hsin S. Lee, Georgia Institute of Technology
Zombie: Extending Memory Lifetime by Reviving Dead Blocks
Rodolfo Jardim de Azevedo, State University of Campinas, Brazil
John D. Davis, Microsoft Research
Karin Strauss, Microsoft Research and University of Washington
Parikshit Gopalan, Microsoft Research
Mark Manasse, Microsoft Research
Sergey Yekhanin, Microsoft Research
QuickSAN: A Storage Area Network for Fast, Distributed, Solid State Disks
Adrian M. Caulfield, University of California, San Diego
Steven Swanson, University of California, San Diego
Session 6B: Simulation and Analysis Techniques
Chair: Joel Emer, Intel/MIT
ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems
Daniel Sanchez, MIT CSAIL
Christos Kozyrakis, Stanford
GPUWattch: Enabling Energy Optimizations in GPGPUs
Jingwen Leng, The University of Texas at Austin
Tayler Hetherington, University of British Columbia
Ahmed ElTantawy, University of British Columbia
Syed Gilani, University of Wisconsin‚ Madison
Nam Sung Kim, University of Wisconsin–Madison
Tor M. Aamodt, University of British Columbia/Stanford University
Vijay Janapa Reddi, The University of Texas at Austin
Studying Multicore Processor Scaling via Reuse Distance Analysis
Meng-Ju Wu, University of Maryland, College Park
Minshu Zhao, University of Maryland, College Park
Donald Yeung, University of Maryland, College Park
Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior
Kristof Du Bois, Ghent University
Stijn Eyerman, Ghent University
Jennifer B. Sartor, Ghent University
Lieven Eeckhout, Ghent University
Thursday: 1:30pm-2:45pm
Session 7A: Cache Coherence
Chair: Josep Torrellas, University of Illinois
The Locality-Aware Adaptive Cache Coherence Protocol
George Kurian, MIT
Omer Khan, Univ. of Connecticut
Srini Devadas, MIT
A New Perspective for Efficient Virtual-Cache Coherence
Stefanos Kaxiras, Uppsala University
Alberto Ros, Universidad de Murcia
Protozoa: Adaptive Granularity Cache Coherence
Hongzhou Zhao, University of Rochester
Arrvindh Shriraman, Simon Fraser University
Snehasish Kumar, Simon Fraser University
Sandhya Dwarkadas, University of Rochester
Session 7B: Security
Chair: Ruby Lee, Princeton University
On the Feasibility of Online Malware Detection with Performance Counters
John Demme, Columbia University
Matthew Maycock, Columbia University
Jared Schmitz, Columbia University
Adrian Tang, Columbia University
Adam Waksman, Columbia University
Simha Sethumadhavan, Columbia University
Salvatore Stolfo, Columbia University
Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors
Ling Ren, Massachusetts Institute of Technology
Xiangyao Yu, Massachusetts Institute of Technology
Christopher Fletcher, Massachusetts Institute of Technology
Marten van Dijk, Massachusetts Institute of Technology
Srinivas Devadas, Massachusetts Institute of Technology
SurfNoC: A Low Latency and Provably Non-Interfering approach to Secure Networks-On-Chip
Hassan M. G. Wassel (UC Santa Barbara)
Ying Gao (UC Santa Barbara)
Jason K. Oberg (UC San Diego)
Ted Huffmire (Naval Postgraduate School)
Ryan Kastner, (UC San Diego)
Frederic T. Chong (UC Santa Barbara)
Timothy Sherwood (UC Santa Barbara)
3:15pm-4:30pm
Session 8A: Data Centers
Chair: Tom Wenisch, University of Michigan
Virtualizing Power Distribution in Datacenters
Di Wang, The Pennsylvania State University
Chuangang Ren, The Pennsylvania State University
Anand Sivasubramaniam, The Pennsylvania State University
Bubble-Flux: Precise Online QoS Management for Increased Utilization in Warehouse Scale Computers
Hailong Yang, University of California, San Diego
Alex Breslow, University of California, San Diego
Jason Mars, University of California, San Diego
Lingjia Tang, University of California, San Diego
Whare-Map: Heterogeneity in "Homogeneous" Warehouse-Scale Computers
Jason Mars, University of California, San Diego
Lingjia Tang, University of California, San Diego
Robert Hundt, Google
Session 8B: Reliability and Debugging
Chair: Daniel Sorin, Duke University
Deconfigurable Microprocessor Architectures for Silicon Debug Acceleration
Nikos Foutris, University of Athens
Dimitris Gizopoulos, University of Athens
Xavier Vera, Intel Labs Barcelona
Antonio Gonzalez, Intel Labs Barcelona
QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs
Gilles Pokam, Intel
Klaus Danne, Intel
Cristiano Pereira, Intel
Rolf Kassa, Intel
Tim Kranich, Intel
Shiliang Hu, Intel
Justin Gottschlich, Intel
Nima Honarmand, UIUC
Nathan Dautenhahn, UIUC
Sam King, UIUC
Josep Torrellas, UIUC
Non-Race Concurrency Bug Detection Through Order-Sensitive Critical Sections
Ruirui Huang, Cornell University
Erik Halberg, Cornell University
G. Edward Suh, Cornell University
4:30-4:45: Closing Remarks