Tutorials

Friday, June 20, 2008

Registration: 18:00 - 19:00

Saturady, June 21, 2008

Registration starts at 8:00

Morning (break 10:00 - 10:30)

• T1: Integrated Modeling and Management for Multi-Core Processors (Room 9)
  By Pradip Bose

Afternoon (break 15:00 - 15:30)

• T2: Tutorial on 3D Integration for Computer Architects (Room 4)
  By Gabirel Loh (Georgia Tech) and Yuan Xie (Penn State)


• T3: Transactional Memory: Programming Model and Implementation (Room 7)
  By Yang Ni, Tatiana Shpeisman, Xinmin Tian and Adam Welc

Sunday, June 22, 2008

Registration starts at 7:45

Morning (break 10:00 - 10:30)

• T4: PARSEC Benchmark Suite (Room 7)
  By Christian Bienia (Princeton), Yurong Chen (Intel), Eric Li (Intel) and Jonathan Su (Stanford)

You may also check out the schedules and programs of the workshops.