Pre-silicon performance modeling in the 21st century has quickly evolved, out of technology-driven necessity, into an integrated modeling art or science. No longer is it meaningful for architects to study performance (IPC) sensitivities in isolation, while product quality metrics like power, temperature and reliability are modeled only in late-stage design. With cycle-accurate performance models augmented with the burden of also projecting the above other quality-related metrics, issues related to simulation speed and analysis accuracy get magnified by a large factor. In this tutorial, we propose to present the modern challenge of integrated pre-silicon modeling and validation from the perspective of real industrial microprocessor design projects. We will also examine the techniques to model the benefits (and performance degradations) derived from on-chip power, temperature and reliability management devices within the framework of current generation multi-core integrated models. We will discuss methods of validating pre-silicon integrated models and present real data to illustrate the errors that can result from inadequate high-level abstractions during early-stage modeling. We will cover academic research concepts that have benefited or influenced industrial practice in all aspects of the above problem, and we will point to open research issues and problems that need to be solved – especially in the context of technological changes brought forth by 3D chip integration.
List of Topics:Tutorial Duration: half day (3-4 hours)
Audience: students, researchers and practitioners in power-efficient, reliable microprocessor architectures are welcome to attend.
Key Paper/Prior Tutorial References:Pradip Bose is a Research Staff Member and Manager of the Reliability- and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center at Yorktown Heights, NY. He has been with IBM Research for nearly 25 years and has been involved in the architecture definition and associated pre-silicon modeling of the full range of IBM’s POWER-series microprocessors, beginning with the pioneering RISC super scalar research project in the early eighties (that led to the first POWER-1 and the associated RS/6000 product family). Currently, he is part of the DARPA-funded PERCS project that in part drives the POWER7 microprocessor development work. Pradip has a Ph.D from University of Illinois at Urbana-Champaign and is the author or co-author of over 80 peer-reviewed publications and is currently at the seventh invention achievement plateau level within IBM for his patent-related contributions. He has been actively involved in various IEEE/ACM conference committees and is the past editor-in-chief of IEEE Micro. He has given numerous past tutorials at conferences: ISCA, MICRO, HPCA, Sigmetrics, ICS, VLSI Design, VLSI Test Symposium, International Test Conference, etc. He was a recent invited lecturer at the ACACES-2007 european summer school held at L’aquila, Italy, He is a Fellow of IEEE.
Alper Buyuktosunoglu received MS and PhD degrees in Electrical and Computer Engineering from University of Rochester in 2000 and 2003, respectively. Dr. Buyuktosunoglu is a research staff member at IBM T. J. Watson Research Center. At IBM, he has worked in several areas related to power-aware computer architectures, dynamic power management and high-level power modeling of IBM p-series and z-series microprocessors. His research interests include: high performance, low power adaptive computer architectures and digital circuit design. He is a member of the IEEE.
Hendrik Hamann is a research staff member and manager of the Photonics and Thermal Physics department at IBM T. J. Watson Research Center. He holds a doctorate in Physics and is one of the leading innovators at IBM in the area of infra-red based thermal imaging and measurement of integrated circuits as well as data canter level power and thermal modeling and measurement methodologies. He is a master inventor at IBM and is the author of scores of advanced journal articles and book chapters.
Victor Zyuban is a Research Staff Member and Manager of the Low Power Circuits department at IBM T. J. Watson Research Center. He has a Ph.D from University of Notre Dame and is currently the processor core-level power team lead of the POWER7 microprocessor development project. Victor has been active in numerous IEEE/ACM conference committees and has been involved in several conference tutorials, the most recent one at ISLPED-2007. He has dozens of publications in the low power circuits and microarchitecture area and is the holder of numerous patents.
John Darringer is a distinguished engineer and manager of System-Level Design within the Design Automation department at IBM T. J. Watson Research Center. He has a Ph.D from Carnegie-Mellon University. He is one of the original inventors of IBM’s Logic Synthesis System (LSS) that dates back to the late seventies. Currently, he manages a pre-silicon modeling team that works in collaboration with folks in the computer architecture department to innovate leading edge integrated modeling solutions for next generation multi-core processor chips. He is a Fellow of IEEE.