Presenters: Yang Ni, Tatiana Shpeisman, Xinmin Tian and Adam Welc (Intel Corporation)
Time: Saturday afternoon, June 21, 2008
With single thread performance starting to plateau, HW architects have turned to chip level multiprocessing (CMP) for better performance. Major microprocessor companies are aggressively shipping multi-core products in the mainstream computing market. Moore's law will largely be used to increase HW thread-level parallelism through higher core counts in a CMP environment. CMPs bring new challenges into the design of the software system stack. Today, programmers use lock-based synchronization for concurrency control but composing software modules written using locks can lead to well-known problems such as deadlock and poor scalability. Transactional memory (TM) provides an alternate concurrency control mechanism that avoids the pitfalls of lock-based synchronization while providing scalability.
This tutorial will give a comprehensive overview of transactional memory, present the current state of the art in transactional memory research, and discuss some open research problems. The tutorial will cover a range of topics from programming language constructs for transactional programming and their semantics to low-level details of specific algorithms used to implement these constructs efficiently. We show how to extend mainstream languages such as Java and C++ with transactional constructs and how these constructs alleviate some of the programming issues with locks. We present the fundamentals of implementing software transactional memory algorithms for both Java and C++. We show how to integrate transactional memory with other language and runtime features, such as memory management and I/O, and how to leverage compiler optimizations to reduce transactional memory overheads. We describe the design of the publicly available Intel C/C++ compiler and STM system. We will also cover advanced semantics topics including memory models for transactional memory. Finally, we will present some important open research issues.
Biographies
Yang Ni is a research scientist in Intel's Programming Systems Lab. He has been working on programming languages for platforms from mobile devices to chip multi processors. His current research focuses on transactional memory. He is a major contributor to the Intel C/C++ TM compiler. Yang received his Ph.D. in Computer Science from Rutgers University.
Tatiana Shpeisman is a Senior Research Scientist in Intel’s Programming Systems Lab. Her general research interest lies in finding ways to simplify software development while improving program efficiency. Her current research focuses on the semantics of transactional memory. In the past, she worked on dynamic compilation for managed runtime environments, IPF code generation and compiler support for sparse matrix computations. She holds Ph.D. in Computer Science from University of Maryland, College Park and B.S. in Applied Math from Leningrad Electrical Engineering Institute, Russia..
Xinmin Tian is a Principal Engineer/Compiler Architect at Intel. He leads the Intel(R) C++/Fortran parallelization, OpenMP, vectorization and transactional memory compiler development projects for Intel(R) IA-32, Intel(R) 64, and Itanium(R) multi-core processors.
Adam Welc is a Research Scientist in Intel's Programming Systems Lab. His work is in the area of programming language design and implementation, with specific interests in concurrency control, compiler and run-time system optimizations, transactional processing as well as architectural support for programming languages and applications. Adam received the Master of Science in Computer Science from Poznan University of Technology, Poland, in July 1999. He continued his graduate studies at Purdue University, receiving the Master of Science in Computer Science in May 2003, and the Ph.D. in Computer Science in March 2006.