Sunday, June 15, 2014 |
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PM
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6:00-8:00
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Reception (Salon A/B)
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Monday, June 16, 2014 |
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AM
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8:30-8:45
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Opening Remarks (Marquette I/IV)
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8:45-9:45
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Keynote I (Marquette I/IV): Insight into the MICROSOFT XBOX ONE Technology
Dr. Ilan Spillinger, Corporate Vice President, Technology and Silicon, Microsoft
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9:45-10:15
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Fast Forward Session I (Marquette I/IV)
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10:15-10:45
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Break (Marquette I/IV)
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10:45-12:00
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Session 1 (Marquette I/IV): Machines and Prototypes
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PM
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12:00-1:15
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Lunch (Symphony I - III)
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1:15-2:55
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Session 2A (Marquette I): Resilience
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Session 2B (Marquette IV): Design Space Exploration
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2:55-3:25
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Break (Marquette I/IV)
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3:25-5:05
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Session 3A (Marquette I): Caches
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Session 3B (Marquette IV): GPUs and Parallelism
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6:00-onwards
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Business Meeting (Marquette I/IV)
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Tuesday, June 17, 2014 |
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AM
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8:30-9:30
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Keynote II (Marquette I/IV): Should Computer Architects Take a Closer Look At Today's Most Pervasive Computer System – The Mobile Phone?
Prof. Trevor Mudge, Department of Computer Science and Engineering, University of Michigan
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9:30-10:15
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Fast Forward Session II (Marquette I/IV)
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10:15-10:45
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Break (Marquette I/IV)
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10:45-12:00
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Session 4 (Marquette I/IV): Emerging Technologies
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PM
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12:00-2:00
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Awards Luncheon (Salon A - C)
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2:00-3:15
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Session 5A (Marquette I): NVRAM
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Session 5B (Marquette IV): Datacenters and Cloud
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3:15-3:45
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Break (Marquette I/IV)
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3:45-5:00
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Session 6A (Marquette I): DRAM
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Session 6B (Marquette IV): Circuits and Architecture
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6:00-onwards
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Excursion: Mill City Museum, Minneapolis
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Wednesday, June 18, 2014 |
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AM
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8:30-10:10
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Session 7A (Marquette I): Coherence and Replay
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Session 7B (Marquette IV): Security/OOO Processors
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10:10-10:40
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Break (Marquette I/IV)
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10:40-12:20
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Session 8 (Marquette I/IV): Accelerators
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PM
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12:20-12:35
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Closing Remarks (Marquette I/IV)
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Monday, June 16, 2014
Keynote I: Insight into the MICROSOFT XBOX ONE Technology
Chair: Doug Burger, Microsoft
- Bio: Dr. Ilan Spillinger was instrumental in bringing Kinect for Xbox 360 to market, which continues to proliferate additional innovative programs and products within the Natural User Interface industry. His team's recent efforts include developing the new architecture and silicon design for Xbox One and the new Kinect, which launched in the fall of 2013. Previously, during a six-year tenure with IBM, Dr. Spillinger served as a distinguished engineer and vice president for advanced processor design. In that role he was responsible for development of all Power Architecture-based processors at IBM: server processors, embedded processors, and client-driven solutions. Prior to that, Dr. Spillinger was a principal engineer and manager of the architecture team in Intel Israel, responsible for the definition of x86-based low-cost and low-power microprocessors, specifically the first Intel mobile processor in the Intel Centrino roadmap. Spillinger holds a D.Sc. and M.Sc. in electrical engineering from the Technion Israel Institute of Technology in Haifa, Israel, and joined Microsoft in 2007.
Session 1: Machines and Prototypes
Chair: Mark D. Hill, University of Wisconsin-Madison
- Unifying on-chip and inter-node switching within the Anton 2 network
- A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
- SCORPIO: A 36-Core Research Chip Demonstrating Snoopy Coherence on a Scalable Mesh NoC with In-Network Ordering
Brian Towles, J.P. Grossman, Brian
Greskamp, and David E. Shaw (D. E. Shaw Research)
Andrew Putnam (Microsoft), Adrian M.
Caulfield (Microsoft), Eric S. Chung (Microsoft), Derek Chiou (Microsoft and
University of Texas at Austin), Kypros Constantinides (Amazon), John Demme
(Columbia University), Hadi Esmaeilzadeh (Georgia Institute of Technology),
Jeremy Fowers (Microsoft), Gopi Prashanth Gopal (Microsoft), Jan Gray
(Microsoft), Michael Haselman (Microsoft), Scott Hauck (Microsoft and
University of Washington), Stephen Heil (Microsoft), Amir Hormati (Google),
Joo-Young Kim (Microsoft), Sitaram Lanka (Microsoft), James Larus (EPFL), Eric
Peterson (Microsoft), Simon Pope (Microsoft), Aaron Smith (Microsoft), Jason
Thong (Microsoft), Phillip Yi Xiao (Microsoft), Doug Burger (Microsoft)
Bhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian, Woo-Cheol Kwon, Sunghyun Park, Tushar Krishna, Jim Holt, Anantha P. Chandrakasan, Li-Shiuan Peh (Massachusetts Institute of Technology)
Section 2A: Resilience
Chair: Yuan Xie, Pennsylvania State University
- Avoiding Core's DUE & SDC via Acoustic Wave Detectors and Tailored Error Containment and Recovery
- MemGuard: A Low Cost and Energy Efficient Design to Support and Enhance Memory System Reliability
- GangES: Gang Error Simulation for Hardware Resiliency Evaluation
- Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading
Gaurang Upasani (Universitat Politècnica de Catalunya), Xavier Vera (Intel Barcelona Research Center), Antonio González (Universitat Politècnica de Catalunya / Intel Barcelona Research Center)
Long Chen, Zhao Zhang (Iowa State University)
Siva Kumar Sastry Hari (NVIDIA), Radha Venkatagiri (University of Illinois at Urbana-Champaign), Sarita V. Adve (University of Illinois at Urbana-Champaign), Helia Naeimi (Intel Labs)
Jack Wadden (University of Virginia), Alexander Lyashevsky (AMD Research), Sudhanva Gurumurthi (AMD Research), Vilas Sridharan (RAS Architecture, AMD), Kevin Skadron (University of Virginia)
Section 2B: Design Space Exploration
Chair: Martha Kim, Columbia University
- ArchRanker: A Ranking Approach to Design Space Exploration
- Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures
- SynFull: Synthetic Traffic Models Capturing Cache Coherent Behaviour
- Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor
Tianshi Chen (Chinese Academy of Sciences), Qi Guo (Carnegie Mellon University), Ke Tang (University of Science and Technology of China), Olivier Temam (Inria), Zhiwei Xu (Chinese Academy of Sciences), Zhi-Hua Zhou (Nanjing University), Yunji Chen (Chinese Academy of Sciences)
Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David Brooks (Harvard University)
Mario Badr, Natalie Enright Jerger (University of Toronto)
Ashish Venkat, Dean M. Tullsen (University of California, San Diego)
Section 3A: Caches
Chair: Sandhya Dwarkadas, University of Rochester
- The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup
- SC2: A Statistical Compression Cache Scheme
- The Dirty-Block Index
- Going Vertical in Memory Management: Handling Multiplicity by Multi-policy
Andreas Sembrant, Erik Hagersten, David Black-Schaffer (Uppsala University)
Angelos Arelakis, Per Stenstrom (Chalmers University of Technology)
Vivek Seshadri (Carnegie Mellon University), Abhishek Bhowmick (Carnegie Mellon University), Onur Mutlu (Carnegie Mellon University), Phillip B. Gibbons (Intel Pittsburgh), Michael A. Kozuch (Intel Pittsburgh), Todd C. Mowry (Carnegie Mellon University)
Lei Liu (Chinese Academy of Sciences), Yong Li (University of Pittsburgh), Zehan Cui (Chinese Academy of Sciences), Yungang Bao (Chinese Academy of Sciences), Mingyu Chen (Chinese Academy of Sciences), Chengyong Wu (Chinese Academy of Sciences)
Section 3B: GPUs and Parallelism
Chair: Pradeep Dubey, Intel
- Fine-grain Task Aggregation and Coordination on GPUs
- Enabling Preemptive Multiprogramming on GPUs
- Single-Graph Multiple Flows: Energy Efficient Design Alternative for GPGPUs
- HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
Marc S. Orr (University of Wisconsin-Madison / AMD Research), Bradford M. Beckmann (AMD Research), Steven K. Reinhardt (AMD Research), David A. Wood (University of Wisconsin-Madison / AMD Research)
Ivan Tanasic (Barcelona Supercomputing Center / Universitat Politecnica de Catalunya), Isaac Gelado (NVIDIA Research), Javier Cabezas (Barcelona Supercomputing Center / Universitat Politecnica de Catalunya), Alex Ramirez (Barcelona Supercomputing Center / Universitat Politecnica de Catalunya), Nacho Navarro (Barcelona Supercomputing Center / Universitat Politecnica de Catalunya), Mateo Valero (Barcelona Supercomputing Center / Universitat Politecnica de Catalunya)
Dani Voitsechov, Yoav Etsion (Technion – Israel Institute of Technology)
Simone Campanoni (Harvard University), Kevin Brownell (Harvard University), Svilen Kanev (Harvard University), Timothy M. Jones (University of Cambridge), Gu-Yeon Wei (Harvard University), David Brooks (Harvard University)
Tuesday, June 17, 2014
Keynote II: Should Computer Architects Take a Closer Look At Today's Most Pervasive Computer System – The Mobile Phone?
Chair: Steve Keckler, NVIDIA/University of Texas at Austin
- Bio: Dr. Trevor Mudge received his Ph.D. in Computer Science from the University of Illinois. He is now in the Computer Science and Engineering Department at The University of Michigan, where he served a ten-year term as Director of the Advanced Computer Architecture Laboratory. In 2003 Dr. Mudge was named the Bredt Professor of Computer Engineering. He is the author of numerous papers on computer architecture, programming languages, VLSI design, and computer vision. He has supervised 49 theses in these areas. Dr. Mudge is a Fellow of the IEEE, a member of the ACM, the IET, and the British Computer Society. In addition to his position as a faculty member, he runs Idiot Savants, a chip design consultancy.
Section 4: Emerging Technologies
Chair: Alvin Lebeck, Duke University
- Efficient Digital Neurons for Large Scale Cortical Architectures
- An Examination of the Architecture and System-level Tradeoffs of Employing Steep Slope Devices in 3D CMPs
- STAG: Spintronic-Tape Architecture for GPGPU Cache Hierarchies
James E. Smith (University of Wisconsin-Madison)
Karthik Swaminathan, Huichu Liu, Jack Sampson, Vijaykrishnan Narayanan (Pennsylvania State University)
Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan (Purdue University)
Section 5A: NVRAM
Chair: Yoav Etsion, Technion
- Memory Persistency
- Reducing Access Latency of MLC PCMs through Line Striping
- HIOS: A Host Interface I/O Scheduler for Solid State Disks
Steven Pelley, Peter M. Chen, Thomas F. Wenisch (University of Michigan)
Morteza Hoseinzadeh (Sharif University of Technology), Mohammad Arjomand (Sharif University of Technology), Hamid Sarbazi-Azad (Sharif University of Technology / Institute for Research in Fundamental Sciences)
Myoungsoo Jung (University of Texas at Dallas), Wonil Choi (University of Texas at Dallas), Shekhar Srikantaiah (Qualcomm), Joonhyuk Yoo (Daegu University), Mahmut T. Kandemir (Pennsylvania State University)
Section 5B: Datacenters and Cloud
Chair: Nacho Navarro, U. Politecnica de Catalunya
- Towards Energy Proportionality for Large-Scale Latency-Critical Workloads
- SleepScale: Runtime Joint Speed Scaling and Sleep States Management for Power Efficient Data Centers
- Optimizing Virtual Machine Consolidation Performance on NUMA Server Architecture for Cloud Workloads
David Lo (Stanford University), Liqun Cheng (Google), Rama Govindaraju (Google), Luiz André Barroso (Google), Christos Kozyrakis (Stanford University)
Yanpei Liu (University of Wisconsin-Madison), Stark C. Draper (University of Toronto), Nam Sung Kim (University of Wisconsin-Madison)
Ming Liu, Tao Li (University of Florida)
Section 6A: DRAM
Chair: Fred Chong, University of California at Santa Barbara
- Row-Buffer Decoupling: A Case for Low-Latency DRAM Microarchitecture
- Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation
- Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors
Seongil O (Seoul National University), Young Hoon Son (Seoul National University), Nam Sung Kim (University of Wisconsin-Madison), Jung Ho Ahn (Seoul National University)
Tao Zhang (Pennsylvania State University / NVIDIA), Ke Chen (Oracle), Cong Xu (Pennsylvania State University), Guangyu Sun (Peking University), Tao Wang (Peking University), Yuan Xie (Pennsylvania State University)
Yoongu Kim (Carnegie Mellon University), Ross Daly, Jeremie Kim (Carnegie Mellon University), Chris Fallin, Ji Hye Lee (Carnegie Mellon University), Donghyuk Lee (Carnegie Mellon University), Chris Wilkerson (Intel Labs), Konrad Lai, Onur Mutlu (Carnegie Mellon University)
Section 6B: Circuits and Architecture
Chair: Carole-Jean Wu, Arizona State University
- Architecture Implications of Pads as a Scarce Resource
- Increasing Off-Chip Bandwidth in Multi-Core Processors with Switchable Pins
- A Low Power and Reliable Charge Pump Design for Phase Change Memories
Runjie Zhang (University of Virginia), Ke Wang (University of Virginia), Brett H. Meyer (McGill University), Mircea R. Stan (University of Virginia), Kevin Skadron (University of Virginia)
Shaoming Chen, Yue Hu, Ying Zhang, Lu Peng, Jesse Ardonne, Samuel Irving, Ashok Srivastava (Louisiana State University)
Lei Jiang, Bo Zhao, Jun Yang, Youtao Zhang (University of Pittsburgh)
Wednesday, June 18, 2014
Section 7A: Coherence and Replay
Chair: James Laudon, Google
- Fractal++: Closing the Performance Gap between Fractal and Conventional Coherence
- OmniOrder: Directory-Based Conflict Serialization of Transactions
- Pacifier: Record and Replay for Relaxed-Consistency Multiprocessors with Distributed Directory Protocol
- Replay Debugging: Leveraging Record and Replay for Program Debugging
Gwendolyn Voskuilen, T. N. Vijaykumar (Purdue University)
Xuehai Qian (University of California, Berkeley), Benjamin Sahelices (Universidad de Valladolid), Josep Torrellas (University of Illinois at Urbana-Champaign)
Xuehai Qian (University of California, Berkeley), Benjamin Sahelices (Universidad de Valladolid), Depei Qian (Beihang University)
Nima Honarmand, Josep Torrellas (University of Illinois at Urbana-Champaign)
Section 7B: Security/OOO Processors
Chair: Mohit Tiwari, University of Texas at Austin
- The CHERI capability model: Revisiting RISC in an age of risk
- CODOMs: Protecting Software with Code-centric Memory Domains
- EOLE: Paving the Way for an Effective Implementation of Value Prediction
- Improving the Energy Efficiency of Big Cores
Jonathan Woodruff (University of Cambridge), Robert N. M. Watson (University of Cambridge), David Chisnall (University of Cambridge), Simon W. Moore (University of Cambridge), Jonathan Anderson (University of Cambridge), Brooks Davis (SRI International), Ben Laurie (Google UK Ltd), Peter G. Neumann (SRI International), Robert Norton (University of Cambridge), Michael Roe (University of Cambridge)
Lluís Vilanova (Barcelona Supercomputing Center / Universitat Politècnica de Catalunya / Technion – Israel Institute of Technology), Muli Ben-Yehuda (Technion - Israel Institute of Technology), Nacho Navarro (Barcelona Supercomputing Center / Universitat Politècnica de Catalunya), Yoav Etsion (Technion – Israel Institute of Technology), Mateo Valero (Barcelona Supercomputing Center / Universitat Politècnica de Catalunya)
Arthur Perais, André Seznec (IRISA/INRIA)
Kenneth Czechowski (Georgia Institute of Technology), Victor W. Lee (Intel), Ed Grochowski (Intel), Ronny Ronen (Intel), Ronak Singhal (Intel), Richard Vuduc (Georgia Institute of Technology), Pradeep Dubey (Intel)
Section 8: Accelerators
Chair: Boris Grot, University of Edinburgh
- General-Purpose Code Acceleration with Limited-Precision Analog Computation
- Race Logic: A Hardware Acceleration for Dynamic Programming Algorithms
- Eliminating Redundant Fragment Shader Executions on a Mobile GPU via Hardware Memoization
- WebCore: Architectural Support for Mobile Web Browsing
Renée St. Amant (University of Texas at Austin), Amir Yazdanbakhsh (Georgia Institute of Technology), Jongse Park (Georgia Institute of Technology), Bradley Thwaites (Georgia Institute of Technology), Hadi Esmaeilzadeh (Georgia Institute of Technology), Arjang Hassibi (University of Texas at Austin), Luis Ceze (University of Washington), Doug Burger (Microsoft Research)
Advait Madhavan, Timothy Sherwood, Dmitri Strukov (University of California, Santa Barbara)
Jose-Maria Arnau (Universitat Politecnica de Catalunya), Joan-Manuel Parcerisa (Universitat Politecnica de Catalunya), Polychronis Xekalakis (Intel)
Yuhao Zhu, Vijay Janapa Reddi (The University of Texas at Austin)