Workshops and Tutorials

 Workshops and Tutorials

Welcoming Remarks

Yale Patt, General Chair
Dirk Grunwald, Program Chair

 Keynote

 Burton J. Smith, Cray, Inc

 Session: Processor Pipelines
 Session Chair: Krste Asanovic

• The Optimum Pipeline Depth for a Microprocessor
  A. Hartstein, T. R. Puzak
• The Optimal Useful Logic Depth Per Pipeline Stage is 6-8 FO4
  M.S. Hrishikesh , Norman P. Jouppi , Keith I. Farkas , Doug Burger , Stephen W. Keckler, Premkishore Shivakumar
• Increasing Processor Performance by Implementing Deeper Pipelines
  Eric Sprangle , Doug Carmean

Processor Scheduling
Session Chair: Douglas Carmean

• Efficient Dynamic Scheduling Through Tag Elimination
  Dan Ernst, Todd Austin, University of Michigan
• Slack: Maximizing Performance Under Technological Constraints
  Brian Fields, Rastislav Bodik, Mark Hill
• A Large, Fast Instruction Window for Tolerating Cache Misses
  Alvin R. Lebeck, Jinson Koppanalil, Tong Li, Jaidev Patwardhan, Eric Rotenberg
• An Instruction Set Architecture and Microarchitecture for Instruction Level Distributed Processing
  Ho-Seop Kim, James E. Smith

 Keynote

 Bob Colwell, R&E Colwell & Associates, Inc.

Safety and Reliability
Session Chair: Kourosh Gharachorloo

• Transient Fault Recovery Using Simultaneous Multithreading
  T. N. Vijaykumar, Irith Pomeranz, Karl K. Cheng
• Detailed Design and Implementation of Redundant Multithreading Alternatives
  Shubhendu S. Mukherjee, Michael Kontz, Steven K. Reinhardt
• ReVive : Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
  Milos Prvulovic, Zheng Zhang, Josep Torrellas
• SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
  Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood

Power Aware Architecture
Session Chair: Sarita Adve

• Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines
  Seongmoo Heo, Ken Barr, Mark Hampton, and Krste Asanovic
• Drowsy Caches: Techniques for Reducing Leakage Power
  Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor Mudge
• Sim-GALS: A Globally Asynchronous-Locally Synchronous Processor Simulation Environment
  Diana Marculescu

Memory Systems
Session Chair: Margaret Martonosi

• Using a User-Level Memory Thread for Correlation Prefetching
  Yan Solihin , Jaejin Lee, Josep Torrellas
• Avoiding Initialization Misses to the Heap
  Jarrod A. Lewis, Bryan Black, Mikko H. Lipasti
• Going the Distance for TLB Prefetching: An Application-driven Study
  Gokul B. Kandiraju, Anand Sivasubramaniam

Dynamic Optimization
Session Chair: Dirk Grunwald

• Timekeeping in the Memory System: An Efficient Approach to Predicting and Optimizing Memory Behavior
  Zhigang Hu  Stefanos Kaxiras, Margaret Martonosi
• Implementing Optimizations at Decode Time
  Ilhyun Kim, Mikko Lipasti
• Managing Configurable Hardware via Dynamic Working Set Analysis
  Ashutosh S. Dhodapkar, James E. Smith

Data and Storage Networks
Session Chair: Seth Goldstein

• Queue-Pair IP: A Hybrid Architecture for System Area Networks
  Philip Buonadonna , David Culler
• VI-Attached Database Storage
  Yuanyuan Zhou, Suresh Jagannathan, Angelos Bilas ,
  Cezary Dubnicki, James F Philbin, Kai Li,

Vector Architectures
Session Chair: Mateo Valero

• Speculative Dynamic Vectorization
  Alex Pajuelo, Antonio Gonzalez, Mateo Valero
• Tarantula: A Vector Extension to the Alpha Architecture
  Roger Espasa, Federico Ardanaz, Joel Emer, Stephen Felix, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Geoff Lowney, Matt Mattina, Andre Seznec

Supporting Deep Speculation
Session Chair: Artur Klauser

• Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
  André Seznec, Stephen Felix, Venkata Krishnan,Yanakis Sazeides,
• Difficult-Path Branch Prediction Using Subordinate Microthreads
  Robert S. Chappell, Francis Tseng, Adi Yoaz,  Yale N. Patt,
• A Scalable Instruction Queue Using Dependence Chains
  Steven E. Raasch , Nathan L. Binkert , Steven K. Reinhardt