ISCA 2006
Final Program

Monday June 19, 2006

Chair: Mateo Valero, UPC and BSC

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

Jongman Kim, Penn State

Chrysostomos A. Nicopoulos, Penn State

Dongkook Park, Penn State

N. Vijaykrishnan, Penn State

Mazin S. Yousif, Intel Corp.

Chita R. Das, Penn State

 The BlackWidow High-Radix Clos Network

Steve Scott, Cray

Dennis Abts, Cray

John Kim, Stanford University

Bill Dally, Stanford University

Memory Model = Instruction Reordering + Store Atomicity

Arvind, MIT

Jan Willem Maessen, Sun Microsystems

Conditional Memory Ordering

Christoph von Praun, IBM T.J. Watson Research Center

Harold W. Cain, IBM T.J. Watson Research Center

Jong-Deok Choi, IBM T.J. Watson Research Center

Kyung Dong Ryu, IBM T.J. Watson Research Center

Architectural Semantics for Practical Transactional Memory

Austen McDonald, Stanford University

JaeWoong Chung, Stanford University

Brian D. Carlstrom, Stanford University

Chi Cao Minh, Stanford University

Hassan Chafi, Stanford University

Christos Kozyrakis, Stanford University

Kunle Olukotun, Stanford University

Ensemble-level Power Management for Dense Blade Servers

Parthasarathy Ranganathan, HP Labs

Phil Leech, HP Labs

David Irwin, Duke University

Jeff Chase, Duke University

 

Techniques for Multicore Thermal Management: Classification and New Exploration

James Donald, Princeton University

Margaret Martonosi, Princeton University

SODA: A Low-power Architecture for Software Radio

Yuan Lin, University of Michigan

Hyunseok Lee, University of Michigan

Marh Woh, University of Michigan

Yoav Harel, University of Michigan

Scott Mahlke, University of Michigan

Trevor Mudge, University of Michigan

Chaitali Chakrabarti, Arizona State University

Krisztián Flautner, ARM

 

An Integrated Framework for Dependable and Revivable Architecture Using Multicore Processors

Weidong Shi, Georgia Tech

Hsien-Hsin S. Lee, Georgia Tech

Laura Falk, University of Michigan

Mrinmoy Ghosh, Georgia Tech

Multiple Instruction Stream Processor

Richard A. Hankins, Intel Corp.

Gautham N. Chinya, Intel Corp.

Jamison D. Collins, Intel Corp.

Perry H. Wang, Intel Corp.

Ryan Rakvic, United States Naval Academy

Hong Wang, Intel Corp.

John P. Shen, Intel Corp.

Panel Session: "System 2020: Computer Architecture Grand Research Challenges"

Mary Jane Irwin (Penn State), David Patterson (UC-Berkeley), John P. Shen (Intel Corp.)

Tuesday June 20, 2006

Chair: Per Stenstrom

Design and Management of 3D Chip Multiprocessors using Network-in-Memory

Feihui Li, Penn State

Chrys Nicopoulos, Penn State

Tom Richardson, Penn State

Yuan Xie, Penn State

Narayanan Vijaykrishnan, Penn State

Mahmut Kandemir, Penn State

Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification

Alok Garg, University of Rochester

M. Wasiur Rashid, University of Rochester

Michael Huang, University of Rochester

SESSION 5B: CACHE DESIGN I
Chair: Ronny Ronen, Intel Corp.
 

Balanced-Cache: Reducing Conflict Misses of Direct-Mapped Caches through Programmable Decoders

Chuanjun Zhang, University of Missouri-Kansas City

A Case for MLP-Aware Cache Replacement

Moinuddin K. Qureshi, University of Texas at Austin

Daniel N. Lynch, University of Texas at Austin

Onur Mutlu, University of Texas at Austin

Yale N. Patt, University of Texas at Austin

Improving Cost, Performance, and Security of Memory Encryption and Authentication

Chenyu Yan, Georgia Tech

Brian Rogers, North Carolina State University

Daniel Englender, Georgia Tech

Yan Solihin, North Carolina State University

Milos Prvulovic, Georgia Tech

A Scalable Architecture for High-Throughput Regular- Expression Pattern Matching

Benjamin C. Brodie, Exegy

Ron K. Cytron, Exegy

David E. Taylor, Exegy

Chisel: A Storage-Efficient, Collision-Free Hash-based Network Processing Architecture

Jahangir Hasan, Purdue University

Srihari Cadambi, NEC Laboratories

Venkata Jakkula, NEC Laboratories

Srimat Chakradhar, NEC Laboratories

SESSION 6B: MULTITHREADING
Chair: Susan Eggers, Unviersity of Washington
 

Tolerating Dependences Between Large Speculative Threads Via Sub-Threads

Christopher B. Colohan, Google

Anastassia Ailamaki, Carnegie Mellon University

J. Gregory Steffan, University of Toronto

Todd C. Mowry, Carnegie Mellon University and Intel Research Pittsburgh

Bulk Disambiguation of Speculative Threads in Multiprocessors

Luis Ceze, University of Illinois

James Tuck, University of Illinois

Calin Cascaval, IBM Research

Josep Torrellas, University of Illinois

Learning-Based SMT Processor Resource Distribution via Hill-Climbing

Seungryul Choi, University of Maryland

Donald Yeung, University of Maryland

Spatial Memory Streaming

Stephen Somogyi, Carnegie Mellon University

Thomas F. Wenisch, Carnegie Mellon University

Anastassia Ailamaki, Carnegie Mellon University

Babak Falsafi, Carnegie Mellon University

Andreas Moshovos, University of Toronto

Cooperative Caching for Chip Multiprocessors

Jichuan Chang, University of Wisconsin-Madison

Gurindar S. Sohi, University of Wisconsin-Madison

SESSION 7B: POTPOURRI
Chair: Daniel Jiménez, Rutgers University
 

Reducing Startup Time in Co-Designed Virtual Machines

Shiliang Hu, University of Wisconsin

James E. Smith, University of Wisconsin

TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time

Qing Yang, University of Rhode Island

Wijun Xiao, University of Rhode Island

Jin Ren, University of Rhode Island
 

Program Demultiplexing: Data-flow Execution of Methods in Sequential Programs

Saisanthosh Balakrishnan, University of Wisconsin

Gurindar S. Sohi, University of Wisconsin

Area-Performance Trade-offs in Tiled Dataflow Architectures

Steven Swanson, University of Washington

Andrew Putnam, University of Washington

Martha Mercaldi, University of Washington

Ken Michelson, University of Washington

Andrew Petersen, University of Washington

Andrew Schwerin, University of Washington

Mark Oskin, University of Washington

Susan Eggers, University of Washington

SESSION 8B: CACHE COHERENCE
Chair: Alex Veidenbaum, University of California Irvine
 

Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors

Karin Strauss, University of Illinois

Xiaowei Shen, IBM Research

Josep Torrellas, University of Illinois

Interconnect-Aware Coherence Protocols for Chip Multiprocessors

Liqun Cheng, University of Utah

Naveen Muralimanohar, University of Utah

Karthik Ramani, University of Utah

Rajeev Balasubramonian, University of Utah

John B. Carter, University of Utah

Wednesday June 21, 2006

Chair: David Kaeli, Northeastern University

Distributed Arithmetic on a Quantum Multicomputer

Rodney Van Meter, Keio University

W. J. Munro, HP Labs

Kae Nemoto, NII

Kohei M. Itoh, Keio University

Interconnection Networks for Scalable Quantum Computers

Nemanja Isailovic, UC Berkeley

Yatish Patel, UC Berkeley

Mark Whitney, UC Berkeley

John Kubiatowicz, UC Berkeley

Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing

Darshan D. Thaker, UC Davis

Tzvetan S. Metodi, UC Davis

Andrew W. Cross, MIT

Isaac L. Chuang, MIT

Frederic T. Chong, UC Santa Barbara