Previous ISCAs: ISCA 2003 ISCA 2002 ISCA 2001

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Advance Program

Sunday, June 20, 2004 19:00 Welcome Reception (Pavillion) Monday, June 21, 2004 8:15-8:30 Opening Address (Festsaal) 8:30-9:30 Keynote 1 (Festsaal) Computer Architecture: Challenges and Opportunities for the Next Decade Tilak Agerwala, IBM 9:30-10:00 Break 10:00-11:30 Session 1: Architecture Evaluations (Festsaal) Chair: Yale Patt, UT Austin Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams Michael Taylor, Walter Lee, Jason Miller, David Wentzlaff, Benjamin Greenwald, Volker Strumpen, Nathan Shnidman, Ian Bratt, Henry Hoffmann, Jason Kim, Arvind Saraf James Psota, Jonathan, Matthew Frank, Saman Amarasinghe, and Anant Agarwal, MIT Evaluating the Imagine Stream Architecture Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das, Computer Systems Laboratory, Stanford University Field-testing IMPACT EPIC Research Results in Itanium 2 John W. Sias, Sain-zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, and Wen-mei W. Hwu - University of Illinois at Urbana-Champaign 11:30-13:30 Lunch (Cocktail Lounge/Atrium) 13:30-15:30 Session 2A: Parallelism in Microarchitectures (Festsaal) Chair: Wen-Mei Hwu, Univ. of Illinois, Urbana Champaign Wire Delay is not a Problem for SMT (in the Near Future) Zeshan Chishti and T. N. Vijaykumar, Purdue The Vector-Thread Architecture Ronny Krashinsky, Christopher Batten, Steve Gerding, Mark Hampton, Brian Pharris, Jared Casper, Krste Asanovic, MIT Single-ISA Heterogeneous Multi-Core Architecture Designs for Multithreaded Workload Performance Rakesh Kumar and Dean M. Tullsen, UCSD, Parthasarathy Ranganathan, Norman P. Jouppi, and Keith I. Farkas, HP Labs Microarchitecture Optimizations for Exploiting Memory-Level Parallelism Yuan Chou, Brian Fahs, and Santosh Abraham, Sun Microsystems 13:30-15:30 Session 2B: Memory Consistency (Pallaishalle) Chair: Mark Hill, University of Wisconsin, Madison Memory Ordering: A Value-based Approach Harold W. Cain and Mikko H. Lipasti, Univ. of Wisconsin Transactional Memory Coherence and Consistency Lance Hammond and Vicky Wong, Stanford University Mike Chen, Stanford University / Intel, Ben Hertzberg, Brian Carlstrom, Manohar Prabhu, Honggo Wijaya, Christos Kozyrakis, and Kunle Olukotun, Stanford University TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model Sudheendra Hangal, Sun Microsystems India Pvt. Limited, Durgam Vahia, Chaiyasit Manovit, Joseph Lu, and Sridhar Narayanan, Sun Microsystems, Sunnyvale, CA SMTp: An Architecture for Next-generation Scalable Multi-threading Mainak Chaudhuri, Computer Systems Laboratory, Cornell University, Mark Heinrich, School of Computer Science, University of Central Florida 15:30-16:00 Break 16:00-18:00 Panel (Festsaal) Supporting ILP in tiled architectures: wasted effort, or a good idea? Chair: Anant Agarwal, MIT Panelists: Christoforos Kozyrakis, Stanford Doug Burger, UT Austin Sriram Vajapeyam, Oracle Corp. Krste Asanovic, MIT Fred Chong, UC Davis 18:00- ACM SIGARCH & IEEE TCCA Business Metting (Festsaal) cancelled Staatsempfang / State Reception Tuesday, June 22, 2004 8:30-9:30 Keynote 2 (Festsaal) High Performance Throughput Computing Marc Tremblay, Sun Microsystems 9:30-10:00 Break 10:00-11:30 Session 3A: Power and Energy (Festsaal) Chair: Josep Torrellas, Univ. of Illinois, Urbana Champaign Spreading Slack for Optimal Energy-Performance Tradeoffs for Multimedia Applications Christopher J. Hughes, Intel Sarita V. Adve, University of Illinois at Urbana-Champaign Synchroscalar: A Multiple Clock Domain Power-Aware Tile-Based Embedded Processor John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, and Erik Czernikowski, University of California at Davis, Leslie W. Jones IV, California Polytechnic State University, San Luis Obispo, Dean Copsey, University of California at Davis, Diana Keen, California Polytechnic State University, San Luis Obispo, Venkatesh Akella, and Frederic T. Chong, University of California at Davis Power Awareness through Selective Dynamically Optimized Traces Roni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, and Avi Mendelson, Intel Labs 10:00-11:30 Session 3B: Interconnect and I/O (Pallaishalle) Chair: Steve Scott, Cray X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs Lakshmi N Bairavasundaram, Muthian Sivathanu, Andrea C Arpaci-Dusseau, and Remzi H Arpaci-Dusseau, University of Wisconsin-Madison Low-Latency Virtual-Channel Routers for On-Chip Networks Robert Mullins, Andrew West, and Simon Moore, University of Cambridge Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism V.Puente, J.A.Gregorio, F.Vallejo, and R.Beivide, Computer Architecture Research Group, University of Cantabria, Spain 11:30-13:30 Award Lunch (Dachgarten Restaurant) 13:30-14:30 Session 4A: Compression and Debugging (Festsaal) Chair: Norm Jouppi, HP Adaptive Cache Compression for High-Performance Processors Alaa R. Alameldeen and David A. Wood, University of Wisconsin iWatcher: Efficient Architecture Support for Software Debugging Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, and Josep Torrellas (UIUC) 13:30-14:30 Session 4B: Superscalars (Pallaishalle) Chair: Tom Conte, North Carolina State University From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation Sami YEHIA and Olivier TEMAM, LRI, Paris-South University, France. Prophet-Critic Hybrid Branch Prediction Ayose Falcon, UPC, Jared Stark, Intel, Alex Ramirez, UPC, Konrad Lai, Intel, Mateo Valero, UPC 15:00 Guided Tour through the "Deutsches Museum" / Historical Computers (Departure: 14:45) General Information about the "Deutsches Museum" Collection of Historical Computers 19:00 Conference Dinner / Bavarian Evening (Hofbräuhaus München, Platzl 9) Wednesday, June 23, 2004 9:00-10:30 Session 5A: Support for Reliability (Festsaal) Chair: Mikko Lipasti, Univ. of Wisconsin, Madison Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor Christopher Weaver, Joel Emer, and Shubhendu S. Mukherjee, Intel Corporation, Steven K. Reinhardt, Intel Corporation and Univ. of Michigan The Case for Lifetime Reliability-Aware Microprocessors Jayanth Srinivasan, Sarita V. Adve, University of Illinois, Urbana-Champaign, Dept. of Computer Science, Pradip Bose and Jude A. Rivers, IBM T.J. Watson Research Center Exploiting Resonant Behavior to Reduce Inductive Noise Michael D. Powell and T. N. Vijaykumar, Purdue 9:00-10:30 Session 5B: Register File (Pallaishalle) Chair: Joel Emer, Intel Use-Based Register Caching with Decoupled Indexing J. Adam Butts and Guri Sohi, University of Wisconsin-Madison A Content Aware Integer Register File Organisation Ruben Gonzalez and Adrian Cristal, Universitat Politècnica de Catalunya, Daniel Ortega, HP Labs, Alexander V. Veidenbaum, University of California,IRVINE, Mateo Valero, Universitat Politècnica de Catalunya Physical Register Inlining Mikko H. Lipasti, University of Wisconsin-Madison, Brian Mestan, IBM, Erika Gunadi, University of Wisconsin-Madison 10:30-11:00 Break 11:00-12:00 Session 6A: Performance Methodologies (Festsaal) Chair: Pradip Bose, IBM Modeling Superscalar Processors Tejas Karkhanis and James E. Smith, University of Wisconsin - Madison Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies Lieven Eeckhout, Ghent University, Belgium, Rob Bell Jr., University of Texas at Austin, USA, Bastiaan Stougie and Koen De Bosschere, Ghent University, Belgium, Lizy Kurian John, University of Texas at Austin, USA 11:00-12:00 Session 6B: Microarchitectural Concepts (Pallaishalle) Chair: Mateo Valero, UPC Extended Split Issue Mechanism: Enabling Flexibility in Hardware Implementation of NUAL VLIW DSPs Bharath Iyer, Sadagopan Srinivasan, and Bruce Jacob, Department of Electrical and Computer Engineering, University of Maryland, College Park. A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy Angshuman Parashar, Sudhanva Gurumurthi, and Anand Sivasubramaniam, The Pennsylvania State University 12:00 Adjourn . . .