ISCA 2001 WORKSHOPS (June 30 – July 1)
W1: Workshop on Memory Performance Issues (2 days)
Saturday 9:00 AM – 5:00 PM & Sunday 9:00 AM – 5:00 PM
Organizers: Haldun Hadimioglu (Polytechnic University), David Kaeli (Northeastern University), Jeff Kuskin (Growth Networks), Ashwini Nanda (IBM), and Josep Torrellas (University of Illinois, Urbana).
This workshop combines two existing workshops (Scalable Shared Memory Multiprocessors and Solving the Memory Wall). The goal of this new workshop is to provide a forum for researchers and practitioners from industry and academia to discuss advances in technology, architecture, and algorithms that address the need for scalability in multiprocessors and the growing gap between CPU/network and memory speeds. Both hardware and software approaches to addressing scalability and speed disparities are encouraged. We are especially interested in attracting new, experimental or paper techniques, technologies and algorithms that address these issues. For more information, see http://www.ece.neu.edu/conf/wmpi2000.
W2: Workshop on Complexity-Effective Design (WCED'01) (1 day)
Saturday 9:00 AM – 5:00 PM
Organizers: David Albonesi (Univ. of Rochester) Pradip Bose (IBM), and Subbarao Palacharla (Intel).
Description: The quest for higher performance via deep pipelining (for high clock rate) and speculative, out-of-order execution (for high IPC) has yielded processors with greater performance, but at the expense of much greater design complexity. The costs of higher complexity are many-fold, including increased verification time, higher power dissipation, and reduced scalability with process shrinks/variations. The goal of this workshop is to provide a forum for microarchitects, circuit designers, performance modelers, compiler developers, verification experts, and system designers to discuss and explore hardware/software techniques and tools for creating future designs that are more complexity-effective (CE). For more information, see http://www.ece.rochester.edu/~albonesi/wced01.
W3: EASY: Evaluating and Architecting Systems for Dependability (1 day)
Sunday 9:00 AM – 5:00 PM
Organizers: Kimberly Keaton (Hewlett Packard Lab.) and Steven Lumetta (University of Illinois, Urbana-Champaign)
Although the end customers of systems care about performance, mounting evidence suggests that they care even more about system availability, manageability, reliability, scalability, and security. Despite the importance of these characteristics, benchmarking organizations like SPEC, TPC and SPC do not currently have strategies for evaluating them. The goal of this workshop is to bring together researchers from the computer architecture and dependable systems communities to start a dialog on techniques for evaluating computer system dependability. For more information, see http://www.crhc.uiuc.edu/EASY/