ISCA
TECHNICAL PROGRAM: (July 2 – July 4)
Monday, July 2, 2001
8:45 AM – 10:15 AM
PLENARY SESSION
Opening Remarks
Keynote Speech: Greg Papadopoulos, CTO, Sun Microsystems
Inc., U.S.A.
10:45 AM - 12:15 noon
SESSION 1
MULTITHREADING AND SPECULATION
Chair: Mateo Valero, Universitat Politecnica de Catalunya, Barcelona,
Spain
Execution-based Prediction Using Speculative Slices, Craig Zilles and Gurindar
Sohi (University of Wisconsin-Madison). (pdf)
Speculative Precomputation: Long-range Prefetching of Delinquent Loads,
Jamison D Collins (UC San Diego), Hong Wang (MRL, Intel), Dean M Tullsen
(UC San Diego), Christopher J Hughes (University of Illinois at Urbana-Champaign),
Yong-fong Lee (MSL, Intel), Dan Lavery (MSL, Intel), John P. Shen (MRL,
Intel).
Dynamically Allocating Processor Resources Between Nearby and Distant ILP,
Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi (University
of Rochester). (ps)
13:45 PM – 15:15 PM
SESSION 2
MEMORY SYSTEM ISSUES
Chair: Mark D. Hill, University of Wisconsin-Madison
Tolerating Memory Latency through Software-Controlled Pre-Execution in
Simultaneous Multithreading Processors, Chi-Keung Luk (Compaq). (ps.gz)
Data Prefetching by Dependence Graph Precomputation, Murali M Annavaram,
Jignesh M Patel, and Edward S Davidson (University of Michigan). (ps)
Concurrency, Latency, or System Overhead: Which Has the Largest Impact
on Uniprocessor DRAM-System Performance?, Vinodh Cuppu and BruceJacob (University
of Maryland). (pdf)
15:45 PM – 17:15 PM
SESSION 3
PROCESSOR ARCHITECTURE
Chair: Dean Tullsen, University of California at San Diego
Focusing Processor Policies via Critical-Path Prediction, Brian A Fields,
Shai Rubin and Rastislav Bodik (University of Wisconsin-Madison). (pdf)
Automated Design of Finite State Machine Predictors for Customized Processors,
Timothy Sherwood and Brad Calder (University of California San Diego).
Better Exploration of Region-Level Value Locality with Integrated Computation
Reuse and Value Prediction, Youfeng Wu, Dong-Yuan Chen, and Jesse Fang
(MRL, Intel).
ACM SIGARCH AND IEEE CS TCCA BUSINESS MEETING
RECEPTION AT THE CITY HALL
Tuesday, July 3, 2001
9:00 AM – 10:00 AM
SESSION 4
COMMUNICATION SUPPORT
Chair: Josep Torrellas, University of Illinois at
Urbana Champaign
CryptoManiac: A Fast Flexible Architecture for Secure Communication, Lisa
Wu, Chris Weaver, and Todd Austin (University of Michigan).
QoS Provisioning in Clusters: An Investigation of Router and NIC Design,
Ki H. Yum, Eun J. Kim, and Chita R. Das (Pennsylvania State
University). (ps)
10:30 AM – 12:00 PM
SESSION 5
CACHE MANAGEMENT
Chair: Doug Burger, University of Texas at Austin
Locality vs. Criticality, Srikanth T Srinivasan (Duke University), Roy
Dz-ching Ju(MRL, Intel), Alvin R Lebeck (Duke University), and Chris Wilkerson
(MRL, Intel). (ps)
Dead-Block Prediction & Dead-Block Correlating Prefetchers, An-Chow
Lai (Purdue University), Cem Fide (Sun Microsystems), and Babak Falsafi
(Carnegie Mellon University). (pdf)
Code Layout Optimizations for Transaction Processing Workloads, Alex Ramirez
(UPC, Spain), Luiz Andre Barroso (Compaq WRL), Kourosh Gharachorloo (Compaq
WRL), Robert Cohn (Compaq), Josep Larriba-Pey (UPC, Spain), Geoff Lowney
(Compaq), and Mateo Valero (UPC, Spain).
12:00 PM – 14:00 PM
AWARD LUNCHEON
14:00 PM – 15:00 PM
SESSION 6A
ARCHITECTURAL IMPACT OF EMERGING TECHNOLOGIES
Chair: Bill Dally, Stanford University
Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies,
Michael Niemier and Peter Kogge (University of Notre Dame) (ps).
NanoFabrics: Spatial Computing Using Molecular Electronics, Seth Copen
Goldstein, and Mihai Budiu (Carnegie Mellon University). (pdf)
14:00 PM – 15:00 PM
SESSION 6B
SHARED-MEMORY MULTIPROCESSORS
Chair: Faye' Briggs, Intel
A Simple Method for Extracting Models from Protocol Code, David J Lie,
Andy Chou, Dawson Engler, and David Dill (Stanford University).
Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization,
Milos Prvulovic (University of Illinois at Urbana-Champaign), Maria Jesus
Garzaran (Universidad de Zaragoza), Lawrence Rauchwerger (Texas A&M University), and Josep Torrellas (University of
Illinois at Urbana-Champaign). (ps)
EXCURSION & BANQUET
Wednesday, July 4, 2001
8:30 AM – 10:00 AM
SESSION 7
ENERGY-EFFECTIVE DESIGNS
Chair: Fredrik Dahlgren, Ericsson, Sweden
Power and Energy Reduction Via Pipeline Balancing, R. Iris Bahar (Brown
University & Compaq) and Srilatha Manne
(Compaq). (ps.gz)
Energy-Effective Issue Logic, Daniele Folegnani and Antonio Gonzalez (Universitat
Politecnica de Catalunya, Spain). (pdf)
Cache Decay: Exploiting Generational Behavior to Reduce Leakage Power,
Stefanos Kaxiras (Bell Labs, Lucent Technologies), Zhigang Hu (Princeton
University), and Margaret Martonosi (Princeton University). (ps)
10:30 AM – 12:00 PM
SESSION 8
PERFORMANCE TOOLS AND EVALUATIONS
Chair: Susan Eggers, University of Washington
Variability in the Execution of Multimedia Applications and Implications
for General-Purpose Architectures, Christopher J. Hughes, Praful Kaul,
Sarita Adve, Rohit Jain, Chanik Park, and Jayanth Srinivasan (University
of Illinois at Urbana-Champaign). (ps) (pdf)
Measuring Experimental Error in Microprocessor Simulation, Rajagopalan
Desikan, Doug Burger, and Stephen W Keckler (University of Texas at Austin).
(ps)
(pdf)
Rapid Profiling via Stratified Sampling, Subramanya Sastry, Rastislav Bodik,
and James Smith (University of Wisconsin-Madison). (ps)
ADJOURN