25th International Symposium on
Computer Architecture

Advance Program


Saturday 27

Sunday 28

Monday 29

Tuesday 30

Wednesday 1









Opening Remarks

S4: Speculation

S8A: Processor Microarch.

S8B: Parallel Machines

Keynote: J. Hennessy

S2: Machine Measurement

S5A: Prediction Techniques

S5B: Memory Managm.

S9: Cache and Memory Systems



S3A: Program Behaviour

S3B: Graphics and I/O

Luncheon (*)


City Tour and Reception

S6: Predication

Welcome Reception

S7: Special 25th Anniversary

T1: Java
T2: Emerging Processor Techniques ...
T3: High-performance I/O Systems
T4: Protocols and Processors



W1: Computer Architecture Education
W2: Performance Analysis PAID
W3: Scalable Shared-memory Multiprocessors
W4: Power-driven Microarchitecture

(*) Conference Luncheon: Maurice Wilkes and Eckert-Mauchly awards



June 27 (Saturday) 8:00 am - 6:00 pm
Workshop 1: Computer Architecture Education
David Kaeli (Northeastern University) and Antonio Gonzalez (Universitat Politècnica de Catalunya) 

June 27 and 28 (Saturday and Sunday) 8:00 am - 6:00 pm
Workshop 2: Performance Analysis and Its Impact in Design (PAID)
Thomas M. Conte (NC State University) and Pradip Bose (IBM T.J. Watson Research Center)

June 27 (Saturday) 8:00 am - 6:00 pm
June 28 (Sunday) 8:00 am - noon
Workshop 3: Seventh Workshop on Scalable Shared-memory Multiprocessors
Organizers :
Ashwini Nanda (IBM T. J. Watson Research Center), Josep Torrellas (University of Illinois at Urbana-Champaign) and Jeff Kuskin (SGI)


June 28 (Sunday) 8:00 pm - 6:00 pm
Workshop 4: Power-driven Microarchitecture
Dirk Grunwald (University of Colorado, Boulder), Trevor Mudge (University of Michigan) and Srilatha Manne (University of Colorado, Boulder)



June 27 (Saturday) 8:00 am - 6:30 pm
Tutorial 1: Java: VM Architecture, Software Architecture, Implementations, and Applications
Lecturer: Wen-Mei Hwu (University of Illinois)


June 28 (Sunday) 8:00 am - 12:30 pm
Tutorial 2: Emerging Processor Techniques for Exploiting Instruction-level Parallelism
Lecturer: Sriram Vajapeyam (Indian Institute of Science)


June 28 (Sunday) 2:00 pm - 6:30 pm
Tutorial 3: High-performance I/O Systems: From Architectures to Applications
Lecturer: Alok Chouddhary (Northwestern University)


June 28 (Sunday) 2:00 pm - 6:30 pm
Tutorial 4: How to Make Protocols and Processors Work Right Every Time
Lecturers: Arvind and Martin Rinard (Laboratory for Computer Science, MIT)



June 28 (Sunday)

6:00 pm
Welcome Reception


June 29 (Monday)

8:15 am - 8:30 am
Opening Remarks
Mateo Valero (UPC)
Guri Sohi (University of Wisconsin-Madison)


8:30 am - 9:30 am
Session 1: Keynote Speech
John Hennessy (Stanford University)
ISCA25: Looking Backward, Looking Forward

9:30 am - 11:30 am
Session 2: Machine Measurement

Memory System Characterization of Commercial Workloads
Luiz Andre Barroso, Kourosh Gharachorloo and Edouard D. Bugnion
DEC Western Research Laboratory

Performance Characterization of the Quad Pentium Pro SMP Using OLTP Workloads
Kimberly Keeton (1), David A. Patterson (1), Yong Qiang He (2), Roger C. Raphael (2) and Walter E. Baker (2)
(1) UC Berkeley and (2) Informix Software, Inc.

Execution Characteristics of Desktop Applications on Windows NT
Dennis C. Lee, Patrick J. Crowley, Jean-Loup J. Baer, Thomas E. Anderson and Brian N. Bershad
University of Washington

An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors
Jack L. Lo (1), Luiz Andre Barroso (2), Susan J. Eggers (1), Kourosh Gharachorloo (2), Henry M. Levy (1) and Sujay S. Parekh (1)
(1) University of Washington and (2) Digital Equipment Corporation, Western Research Laboratory


11:30 am - 12:00 am -- Coffee Break

12:00 am - 1:30 pm
Session 3A: Program Behaviour

An Analysis of Correlation and Predictability: What Makes Two-level Branch Predictors Work
Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
University of Michigan

Branch Prediction Based on Universal Data Compression Algorithms
Eitan Federovsky, Meir Feder, and Shlomo Weiss
Tel Aviv University

Modeling Program Predictability
Yiannakis Sazeides and James E. Smith
University of Wisconsin-Madison


12:00 am - 1:30 pm
Session 3B: Graphics and IO

Multi-level Texture Caching for 3D Graphics Hardware
Michael Cox (1), Narendra Bhandari (2) and Michael Shantz (2)
(1) MRJ/NASA Ames Research Center and Intel Microcomputer Research Labs and (2) Intel Microcomputer Research Labs

Switcherland: A QoS Communication Architecture for Workstation Clusters
Hans Eberle and Erwin Oertli
Swiss Federal Institute of Technology (ETH)

Declustered Disk Array Architectures with Optimal and Near-optimal Parallelism
Guillermo A. Alvarez (1), Walter A. Burkhard (1), Larry J. Stockmeyer (2) and Flaviu Cristian (1)
(1)University of California, San Diego and (2) IBM Almaden Research Center

1:30 pm - 3:30 pm -- Lunch Break

3:30 pm - night -- City Tour and Reception

June 30 (Tuesday)

8:30 am - 10:00 am
Session 4: Speculation

Confidence Estimation for Speculation Control
Dirk Grunwald, Artur Klauser, Srilatha Manne and Andrew Pleszkun
University of Colorado

Pipeline Gating: Speculation Control For Energy Reduction
Srilatha Manne, Artur Klauser and Dirk Grunwald
University of Colorado

Memory Dependence Prediction using Store Sets
George Z. Chrysos and Joel S. Emer
Digital Equipment Corporation


10:00 am - 10:30 am -- Coffee Break

10:30 am - 12:00 pm
Session 5A: Prediction Techniques

Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction
Toni Juan, Sanji Sanjeevan and Juan J. Navarro
Universitat Politècnica de Catalunya

Accurate Indirect Branch Prediction
Karel Driesen and Urs Hölzle
University of California Santa Barbara

Using Prediction to Accelerate Coherence Protocols
Shubhendu S. Mukherjee and Mark D. Hill
University of Wisconsin-Madison


10:30 am - 12:00 pm
Session 5B: Memory Management

Active Pages: A Computation Model for Intelligent Memory
Mark Oskin, Frederic T. Chong, and Timothy Sherwood
Univeristy of California at Davis

Increasing TLB Reach Using Superpages Backed by Shadow Memory
Mark Swanson, Leigh Stoller, and John Carter
University of Utah

Options for Dynamic Address Translation in COMAs
Xiaogang Qiu and Michel Dubois
University of Southern California

12:30 pm - 2:30 pm -- Conference Luncheon
Maurice Wilkes and Eckert-Mauchly awards

2:30 pm - 4:00 pm
Session 6: Predication and Multipath Execution

Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
David I. August (1), Daniel A. Connors (1), Scott A. Mahlke (2), John W. Sias (1), Kevin M. Crozier (1), Ben-Chung Cheng (1), Patrick R. Eaton (1), Qudus B. Olaniran (1) and Wen-Mei Hwu (1)
(1) University of Illinois at Urbana/Champaign and (2) Hewlett-Packard Laboratories

Threaded Multiple Path Execution
Steven Wallace, Brad Calder and Dean M. Tullsen
University of California San Diego

Selective Eager Execution on the PolyPath Architecture
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
University of Colorado


4:00 pm - 4:30 pm -- Coffee Break

4:30 pm - 6:00 pm
Session 7: Special session to commemorate the 25th anniversary of ISCA


6:00 pm - 7:30 pm


8:00 pm - night -- Banquet

July 1 (Wednesday)

9:00 am - 11:00 am
Session 8A: Processor Microarchitecture

Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing
Sanjay J Patel, Marius Evers, Yale N Patt
University of Michigan, Ann Arbor

The Effect of Instruction Fetch Bandwidth on Value Prediction
Freddy Gabbay - EE Technion,
Avi Mendelson - National Semiconductors and Technion.

Dynamic IPC/Clock Rate Optimization
David H. Albonesi
Dept. of Electrical Engineering, University of Rochester

Performance Modeling and Code Partitioning for the DS Architecture
Yinong Zhang (1) and George B. Adams III (2)
(1) Advanced Micro Devices, Inc. and (2) Purdue University

9:00 am - 11:00 am
Session 8B: Parallel Machines

Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Stephen W. Keckler (1), William J. Dally (1), Daniel Maskit (1), Nicholas P. Carter (1), Andrew Chang (1) and Whay S. Lee (2)
(1) Computer Systems Laboratory, Stanford University and (2) Artificial Intelligence Laboratory, MIT

Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance
Gheith A. Abandah and Edward S. Davidson
University of Michigan, Ann Arbor, MI.

Design Choices in the SHRIMP System: An Empirical Study
Matthias A. Blumrich (1), Richard D. Alpert (2), Yuqun Chen (1), Douglas W. Clark (1), Stefanos N. Damianakis (1), Cezary Dubnicki (1), Edward W. Felten (1), Liviu Iftode (3), Kai Li (1), Margaret Martonosi (1) and Robert A. Shillner (1)
(1) Princeton University, (2) NEC Research Institute and (3) Rutgers University

Flexible Use of Memory for Replication/Migration in Cache-coherent DSM Multiprocessors
Vijayaraghavan Soundararajan (1), Mark Heinrich (1), Ben Verghese (2), Kourosh Gharachorloo (2), Anoop Gupta (3) and John Hennessy (1)
(1) Stanford University, (2) DEC Western Research Laboratory and (3) Microsoft Research

11:00 am - 11:30 am -- Coffee Break

11:30 am - 1:00 pm
Session 9: Caches and Memory Systems

Exploiting Spatial Locality in Data Caches using Spatial Footprints
Sanjeev Kumar (a) and Christopher Wilkerson (b)
Princeton University and Microprocessor Research Labs

Low Load Latency through Sum-addressed Memory (SAM)
William Lynch , Chamdani Joseph and Gary Lauterbach
Sun Microsystems

Analytic Evaluation of Shared-memory Parallel Systems with ILP Processors
Daniel J. Sorin (1), Vijay S. Pai (2), Sarita V. Adve (2), Mary K. Vernon (1) and David A. Wood (1)
(1) University of Wisconsin-Madison and (2) Rice University


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