Talk Title: A Return to (Limited) Explicit Dataflow Execution
Abstract: Specialization, accelerators, and machine learning are all the rage. But most of the world’s computing today still uses conventional RISC or CISC CPUs, which expend significant energy to achieve high single-thread performance. Von Neumann ISAs have been so successful because they provide a clean conceptual target to software while running the complete gamut of algorithms reasonably well. We badly need clean new abstractions that utilize fine-grain parallelism and run energy efficiently. Prior work (such as the UT-Austin TRIPS EDGE ISA and others) showed how to form blocks of computation containing limited-scope dataflow graphs, which can be thought of as small structures (DAGs) mapped to silicon. We will describe some post-TRIPS work that addresses the limitations of the original ISA, and how those extensions can provide energy-efficient execution for single threads compared to a conventional out-of-order superscalar design. We will also describe a specific microarchitecture based on these extensions, and show early results. Finally, we will describe how this notion of “structured computation” can be extended to form accelerators dynamically with minor changes to the CPU, or extended to synthesize efficient accelerators that are specialized to a specific workload.
Bio: Doug Burger is a Distinguished Engineer at Microsoft. He currently leads the Silicon and System Futures organization in the Microsoft Research’s NExT division. His team and collaborators founded the Catapult project, which drove FPGAs into wide-spread global use in Microsoft’s cloud. His team is also responsible for architecting the Brainwave system, which is Microsoft’s custom hardware architecture for accelerating deep neural networks, now in large-scale production. Before moving to Microsoft in 2008 he was a Professor of Computer Sciences at the University of Texas at Austin for ten years. At UT-Austin, he co-founded (with Steve Keckler) the TRIPS project, which invented EDGE architectures and NUCA caches, fabricating them into working silicon. He is a past Chair of ACM SIGARCH, and is a co-inventor on 87 U.S. Patents.
Talk Title: Applied Machine Learning at Facebook Scale: Separating Opportunity from Hype
Bio: Kim Hazelwood is a Senior Engineering Manager leading the AI Infrastructure Foundation efforts at Facebook, which focus on the hardware and software platform design and efficiency for Facebook's many applied machine learning-based products and services. Prior to Facebook, Kim held positions including a tenured Associate Professor at the University of Virginia, Software Engineer at Google, and Director of Systems Research at Yahoo Labs. She received a PhD in Computer Science from Harvard University in 2004, and is the recipient of an NSF CAREER Award, the Anita Borg Early Career Award, the MIT Technology Review Top 35 Innovators under 35 Award, and the ACM SIGPLAN 10-Year Test of Time Award. She currently serves on the Board of Directors of CRA, and has authored over 50 conference papers and one book.
Talk Title: Designing Computer Systems for Software 2.0
Abstract: Employing Machine Learning to generate models from data is replacing traditional software development in many applications. This fundamental shift in how we develop software is known as Software 2.0. However, the continued success of Software 2.0 relies on the availability of powerful, efficient and flexible computer systems. This talk will introduce a design paradigm that exploits the characteristics of Software 2.0 to create computer systems that are optimized for both programmability and performance. The key to the design paradigm is a full-stack approach that integrates algorithms, domain-specific languages, advanced compilation technology and new hardware architectures.
Bio: Kunle Olukotun is the Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is well known as a pioneer in multicore processor design and the leader of the Stanford Hydra chip multipocessor (CMP) research project. Olukotun founded Afara Websystems to develop high-throughput, low-power multicore processors for server systems. The Afara multicore processor, called Niagara, was acquired by Sun Microsystems. Niagara derived processors now power all Oracle SPARC-based servers. Olukotun currently directs the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate the use of heterogeneous parallelism in all application areas using Domain Specific Languages (DSLs). Olukotun is a member of the Data Analytics for What’s Next (DAWN) Lab which is developing infrastructure for usable machine learning. Olukotun is an ACM Fellow and IEEE Fellow for contributions to multiprocessors on a chip and multi-threaded processor design and is the recipient of of the 2018 IEEE Harry H. Goode Memorial Award. Olukotun received his Ph.D. in Computer Engineering from The University of Michigan.